Xen Summit 2026 in Munich: RISC-V takes the graveyard slot and wakes the room

Most of our work with the wider Xen community happens in writing, and that works. Honestly, it does. But some topics would take weeks to settle in a chat thread, and some would never come up at all, because nobody would think to raise them in the middle of a normal working day, somewhere between two rebases. Put the same people in one place for three days, and those topics surface on their own, over coffee, in a corridor, or at dinner. No git send-email required.

Vates was one of the sponsors, but the Summit belongs to the Xen community, not to us. (Sponsoring an event doesn’t buy you the room, and that’s precisely what makes the room worth being in.) Silicon vendors, consultancies, universities, and embedded companies were all there, which made the conversations much wider than the ones we have among ourselves. Our own echo chamber has lovely acoustics, but it’s still an echo chamber.

XCP-ng State of the Union (me, Tuesday 10:00). A round of everything that happened since the Spring Meetup in April (five months, roughly three geological eras in our line of work): the market around us, XCP-ng 8.3 LTS and QCOW2, Xen Orchestra 6, the DevOps tooling, then Arm and RISC-V.

One figure I was very happy to put on screen: Vates authored 104 commits to Xen 4.22, 10.9% of the release, making us its third-largest contributor, and more than half of those commits were RISC-V work. You can probably guess which part of that sentence made me happiest.

The RISC-V slide ended with a direct ask to the room: come and review the series, because more reviewers move it faster. Yes, I stood in front of a room full of reviewers and asked for reviewers. Subtle, I am not. Several people came to find me afterwards (more on that below, and it’s the good kind of afterwards).

XCP-ng+Xen status update (Teddy Astie, Tuesday 13:30). Teddy walked through the Xen work behind XCP-ng, and his list is long enough that I’ll give it to you as a list rather than as one heroic sentence (the first draft of this post tried the heroic sentence; the sentence won):

That’s a lot of plates spinning. His slides are on the Summit schedule.

Xen on RISC-V: From Dom0less to xl (Baptiste Le Duc and Oleksii Kurochko, Wednesday 17:00). This is the talk I keep telling people about (whether they asked or not), so it gets its own section.

Anyone who has spoken at a conference knows the last slot of day two. The shared dinner is next, the room is tired, and half the audience is already thinking about beer. In Munich. You can hardly blame them.

Baptiste and Oleksii got the room back anyway.

Baptiste has a sense of showmanship, and the enthusiasm, the stubbornness, and the plain joy the two of them put into this work came through in every slide. The audience applauded in the middle of the talk, more than once. Mid-talk applause, at 17:00 on day two, from hypervisor people. Let that sink in for a second.

And that audience matters. These were committers and maintainers, people who already follow the RISC-V port on the mailing list and know every patch series by name (and, I suspect, by version number). For them, the talk turned Xen on RISC-V from something ethereal into something concrete. From vaporware to hardware, if you’ll forgive me.

The title says the plan, and the plan has two lanes. Upstream, the port goes dom0less first: Xen builds its guests itself at boot, from a static configuration. Downstream, Baptiste and Oleksii already run guests with several vCPUs, on QEMU and on real hardware: a HiFive Premier P550, and a SpacemiT K3 that a community contributor booted independently.

Then comes a full dom0 with the xl toolstack, and that part works too: xl info, xl list, xl create and xl console are all there. Four commands. Doesn’t sound like much? If you’ve typed them on x86 without a second thought, try picturing the work behind each one on a young architecture.

They ended with a demo, pre-recorded in case the conference network let them down, creating a guest from dom0 and talking to it through its console. Is pre-recording cheating? No. That’s experience. Anyone who has ever bet a live demo on conference Wi-Fi knows exactly why, and the knowledge is rarely acquired cheaply.

Baptiste wrote up the P550 story in Xen on RISC-V just ran on real hardware!, including why a core designed before the hypervisor extension was ratified made it harder than it sounds (and "harder than it sounds" is doing a lot of heavy lifting in that sentence). Their slides are on the Summit schedule.

For years, RISC-V meant small boards for hobbyists and embedded work. That is changing, and the reason isn’t a chip. It’s a profile.

RVA23 is a ratified set of mandatory extensions, and the hypervisor extension is one of them. An RVA23 chip is not automatically fast enough to be a server, but it has what virtualisation needs, in a form software can rely on. Once that baseline exists, hardware built for servers can follow, and a server that can’t run a hypervisor is not much use in a datacenter (a very expensive space heater, at best).

So the real question for Xen is whether a type-1 hypervisor will be ready when that hardware arrives. Showing up to the party after the cake is gone is never a great look. That is what Baptiste and Oleksii are working on: making sure we’re there before the candles are lit.

The corridor conversations were at least as exciting as the talks. No slides, no timer, nobody waving a "five minutes left" sign at you.

Several people came over after my talk because, as one of them put it, they had noticed my "unbridled enthusiasm" for RISC-V. Fair enough. Guilty as charged. I’m not sure anyone has ever managed to put a bridle on it, least of all me. From those conversations:

Nothing says "this is getting real" quite like hypervisor people doing their shopping in the corridor.

The atmosphere was friendly and generous, with the kind of good-natured competition where everyone leaves wanting to push a bit harder. Friendly rivalry: the renewable energy of open source.

I’m not a visionary. But I do have a decent memory, and I’ve seen this pattern before: about fifteen years ago, with Arm, a new architecture went from "interesting" to "real" in a few years, and the people who had their software ready early were the ones who mattered. I think RISC-V can go further than Arm did, because the ISA itself is open. Open ISA, open hypervisor: I do like the symmetry.

Is getting ready early a gamble? Sure.

Call it a calculated RISC.

There are enough signals now to say: let’s go. Or, since we were in Munich, los geht’s.

Thanks to the Xen Project team and to Renesas for organising the Summit, and to everyone who came to talk to us, enthusiasm bridled or not.